1. Field of the Invention
The present invention relates to automated design of integrated circuits, and more particularly to the extraction of a logic design from a layout database or a transistor level net list of a logic block.
2. Description of Related Art
Integrated circuits often include complex logic blocks. The design and implementation of such logic blocks is a difficult and time consuming task. It is often desirable to use logic blocks which have been successfully implemented in old integrated circuits, in a new product. For example, a new product that might be more highly integrated including more functions on a single chip, or a new product made using more modem process technologies, may be desired in which a logic block implemented in an old integrated circuit could be directly applied.
However, logic blocks in old integrated circuits often only exist in a physical form. Thus, there is no description of the logic implemented by the logic block at a level of sufficient detail to allow it to be readily ported to a new product or a new process technology. There are existing products on the marketplace that are able to translate a polygon layout description of an integrated circuit into a transistor level net list. See for example, Design Rule Enforcement and Migration DREAM, provided by Sagantec Israel Ltd., of Haifa, Israel. However, the transistor level net list is still insufficient to provide source material for porting the logic block to new process technologies in many circumstances. Also, higher level description of the logic block is necessary to allow hardware emulation and critical path enhancement which might be necessary for successfully porting the old logic block to a new process technology, or to systems requiring different clock rates or other changing parameters of operation.
Accordingly, there is a need for a technique for extracting a logic gate level description of a logic block from a layout database or from a transistor level net list generated from a layout database. Such a technique would enable the recover of substantial intellectual property embodied by layout blocks in older integrated circuit designs. Furthermore, the technique will allow implementation of old designs with denser and faster processes, and with improved characteristics to fit new environments of use.